Can you program in Verilog?

[Privitor]

Hello, guys!
Can any of you help me out with a Verilog program? (stack implementation)

Thanks in advance!

 

[Teflon_Mcgee]

What you need?

It's been a while but I can probably help.

 

[Privitor]

I need the implementation of a stack (Last In First Out). I want to push 16 bytes into it.
reg [7:0] q [0:15];

module stack(clk, reset, load, push, pop, d, qtop, qmiddle);
The header should look like the one above or similar

Inputs:
clk (clock)
reset - empties the stack
load -
d - a 8 bits variable
push -
pop -



Outputs
qtop - 8 bits - the stack is full
qmiddle - 8 bits - indicates the stack is half full

(I don't get it why they should be 8 bits variables. Maybe he wants the values on the last position or the one in the middle)

I need 2 .v files: the stack module and a test module.



Lol, there are 5 more hours to deadline and I get 50 errors in my code.

It's so lame; I should never wait till the last moment ever again.

 

[Privitor]

Yeeeaah! I finished it 1 hour before the deadline. Hahaha!

 

[Teflon_Mcgee]

Well by the time this is straightened out I'm sure the deadline will be up. **EDIT** OH I SEE YOU GOT IT. GOOD JOB

You want the stack to be a max size of 16 bits with each push being one bit or you want each push (each data element) to be 16 bits?

Also the qtop and qmiddle are just flags? 0x00 for false and 0xFF for true?

Are you pushing and poping on the clock edge or just any time you get the push/pop signal? What are load and d?

If you are doing a stack that can be 16 elements deep, each being one bit then I'd start by creating a 16 bit register.

All you have to do is keep track of the top most bit.
every push you increment a counter and every pop you decrement the counter.
The counter represents the index in the register where your pointer is at.

Do not allow a push if counter is > 14 or a pop if counter is < 1

When counter reaches 15 set qtop
When counter reaches 7 set qmiddle

If you break it down it's not bad.
What exactly are you having trouble with? I can still try to help if you're not worried about your deadline.

I need the implementation of a stack (Last In First Out). I want to push 16 bytes into it.
reg [7:0] q [0:15];

module stack(clk, reset, load, push, pop, d, qtop, qmiddle);
The header should look like the one above or similar

Inputs:
clk (clock)
reset - empties the stack
load -
d - a 8 bits variable
push -
pop -



Outputs
qtop - 8 bits - the stack is full
qmiddle - 8 bits - indicates the stack is half full

(I don't get it why they should be 8 bits variables. Maybe he wants the values on the last position or the one in the middle)

I need 2 .v files: the stack module and a test module.



Lol, there are 5 more hours to deadline and I get 50 errors in my code.

It's so lame; I should never wait till the last moment ever again.